Hide navigation sidebar

Hide table of contents sidebar

Skip to content

Toggle site navigation sidebar

Toggle table of contents sidebar

Home

CARP Contributor Homepage

Project Outline

CARP Core Project
CARP Core ISA

Taskboard

Taskboard

Resources and Guides

CARP Videos
ASIC Tools Setup
ASIC VS Setup
ASIC Tools Usage Guides
Toggle navigation of ASIC Tools Usage Guides
ASIC Class Slides
Timing Guides
Toggle navigation of Timing Guides
- Constraints Presentation by Henry Evans
- STA Presentation by Henry Evans
FreeRTOS References
Toggle navigation of FreeRTOS References
- FreeRTOS with RISCV
RISC-V References
Toggle navigation of RISC-V References
Intro to Computer Architecture Slides
Intro to FIFO and uArch Challenge Slides
Intro to ASIC Slides
Arm vs x86 Architecture Slides
BIST Slides

Fall Schedule

CARP Fall 2025 Schedule

Meetings

CARP Meeting 1
CARP Meeting 2
CARP Meeting 3
CARP Meeting 4
CARP Meeting 5
CARP Meeting 6 and 7
CARP Meeting 8
CARP Meeting 9
Verilog Meetup @ Cal Poly

Toggle table of contents sidebar

Verilator Simulation Guide¶

Yosys Synthesis Guide

iVerilog Simulation Guide

Copyright © 2025, CARP

Made with Sphinx and @pradyunsg's Furo