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CARP Project

Home

  • CARP Contributor Homepage

Project Outline

  • CARP Core Project
  • CARP Core ISA

Taskboard

  • Taskboard

Resources and Guides

  • CARP Videos
  • ASIC Tools Setup
  • ASIC VS Setup
  • ASIC Tools Usage Guides
    • Basic Design and Simulation Guide
    • Makefile Guide
    • iVerilog Simulation Guide
    • Verilator Simulation Guide
    • Yosys Synthesis Guide
    • CocoTB Guide
  • ASIC Class Slides
  • Timing Guides
    • Constraints Presentation by Henry Evans
    • STA Presentation by Henry Evans
  • FreeRTOS References
    • FreeRTOS with RISCV
  • RISC-V References
    • CARP Core ISA
    • RISC-V Software Resources
    • RISC-V Privileged Architecture Manual
    • RISC-V Privileged ISA Manual
  • Intro to Computer Architecture Slides
  • Intro to FIFO and uArch Challenge Slides
  • Intro to ASIC Slides
  • Arm vs x86 Architecture Slides
  • BIST Slides

Fall Schedule

  • CARP Fall 2025 Schedule

Meetings

  • CARP Meeting 1
  • CARP Meeting 2
  • CARP Meeting 3
  • CARP Meeting 4
  • CARP Meeting 5
  • CARP Meeting 6 and 7
  • CARP Meeting 8
  • CARP Meeting 9
  • Verilog Meetup @ Cal Poly
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Timing GuidesΒΆ

Constraints Presentation by Henry Evans

STA Presentation by Henry Evans

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Constraints Presentation by Henry Evans
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ASIC Class Slides
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