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CARP Project

Home

  • CARP Contributor Homepage

Project Outline

  • CARP Core Project
  • CARP Core ISA

Taskboard

  • Taskboard

Resources and Guides

  • CARP Videos
  • ASIC Tools Setup
  • ASIC VS Setup
  • ASIC Tools Usage Guides
    • Basic Design and Simulation Guide
    • Makefile Guide
    • iVerilog Simulation Guide
    • Verilator Simulation Guide
    • Yosys Synthesis Guide
    • CocoTB Guide
  • ASIC Class Slides
  • Timing Guides
    • Constraints Presentation by Henry Evans
    • STA Presentation by Henry Evans
  • FreeRTOS References
    • FreeRTOS with RISCV
  • RISC-V References
    • CARP Core ISA
    • RISC-V Software Resources
    • RISC-V Privileged Architecture Manual
    • RISC-V Privileged ISA Manual
  • Intro to Computer Architecture Slides
  • Intro to FIFO and uArch Challenge Slides
  • Intro to ASIC Slides
  • Arm vs x86 Architecture Slides
  • BIST Slides

Fall Schedule

  • CARP Fall 2025 Schedule

Meetings

  • CARP Meeting 1
  • CARP Meeting 2
  • CARP Meeting 3
  • CARP Meeting 4
  • CARP Meeting 5
  • CARP Meeting 6 and 7
  • CARP Meeting 8
  • CARP Meeting 9
  • Verilog Meetup @ Cal Poly
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CARP Meeting 1¶

Note

Welcome to the first CARP meeting! Please make sure to read the Pre-Meeting Brief before attending.

Agenda¶

  • What is CARP?

  • How to Get Involved

  • CARP Core Project

  • Tool Installation

Lab¶

If you’re new here

Install ASIC-Tools and get familiar with the Sky130 PDK.

If you have the tools installed

Please see the muldiv page

Resources¶

  • Sky130 PDK Libraries and Tools Overview

  • Sky130 Foundry-Provided Standard Cell Libraries

Meeting Slides¶

Next
CARP Meeting 2
Previous
CARP Fall 2025 Schedule
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  • CARP Meeting 1
    • Agenda
    • Lab
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    • Meeting Slides