CARP Fall 2025 Schedule

Planned Events

  • “Two Clocks, One Truth”: a deep dive on Async FIFOs (Week 7)

  • Verilog Meetups Event hosted by Verilog Meetup’s Yuri Panchel (TBD)

Weekly Meeting Outline


Week 1: Meeting 1 Kickoff (9/20/25)

  • What CARP is, how to get involved, expectations
  • Core Project Overview
  • Lab: Install tools, run a simulation
Week 2: Meeting 2 - RISC-V Fundamentals (9/24/25)
  • RV32I refresh
  • 5-stage pipeline sketch, control signals, hazards overview
  • Extending to add M, A, C, interrupts, and timer
  • ISA resources and tools
  • Lab: Add and simulate a multiply/divide extension on the ALU
Week 2: Meeting 3 - Pipeline Control Transfer Hazards (9/27/25)
  • Review Jumps and Branches
  • Branch Predictors (static vs dynamic)
  • Implementing CT Hazards in the EEL core
  • Lab: Come up with the specification for a simple dynamic branch predictor
Week 3: Meeting 4 Memory Mapping (10/1/25)
  • RISC-V Memory Map
  • OpenLane Macros
  • Review Interrupts and Branches
  • ISA Resources and Tools
  • Lab: Come up with a RISC-V Memory Map for the CARP Core (if mulitplier done)
Week 3: Meeting 5 RISC-V Context-Switching (10/4/25)
  • RISC-V Control and Status Register
  • Interrupts (software vs hardware)
  • CLINT
  • PLIC
  • Lab: Design a CLINT for the EEL core